1. Field of the Invention
This invention relates to an apparatus and method for image processing and, more particularly, to an image processing apparatus and method for compressing and storing data indicative of a full-color image, such as a photograph having tones (colors), upon partitioning the data into blocks.
2. The Prior Art
The memory capacity necessary for storing a full color image (hereinafter referred to as an "image") such as a photograph in a memory is given by (number of pixels).times.(number of tone bits). As a typical example, a color image composed of 1024 lines (vertical).times.1280 lines (horizontal).times.24 bits per pixel (eight bits for each of the colors R, B and G) is equivalent to 30 megabytes of data. An enormous memory capacity would be required to store such a high-quality color image.
For this reason, a variety of methods of compressing the amount of information have been proposed. Attempts have been made to reduce the required memory capacity by first compressing image information and then storing the compressed information in memory, and subsequently expanding the information when it is read out of the memory to obtain the original image information.
FIG. 32 is a block diagram of an image storing circuit proposed by the JPEG (Joint Photographic Experts Group) of the CCITT/ISO as a method of achieving international standardization of color still-picture coding. The circuit of FIG. 32 is based upon a coding method [see "International Standard for Color Photographic Coding", Hiroshi Yasuda, The Journal of the Institute of Image Electronics Engineers of Japan, Vol. 18, No. 6, pp. 398-407, 1989 (in Japanese)] of a baseline system which combines a discrete cosine transformation (hereinafter referred to as "DCT") and variable length coding (hereinafter referred to as "VLC").
As shown in FIG. 32, pixel data entered from an input terminal 1101 is cut into an 8.times.8 pixel block in a block forming circuit 1102, the data is subjected to a cosine transformation by a DCT circuit 1103, and the transformation coefficients are supplied to a quantization unit 1105. In accordance with quantization-step information supplied by a quantization table 1106, the quantization unit 1105 subjects the transformation coefficients to linear quantization. Of the quantized transformation coefficients, a DC (direct current) coefficient is applied to a predictive coding circuit [hereinafter referred to as a "DPCM" (differential pulse-coded modulation) circuit 1401, which obtains the differential (a prediction error) between this DC coefficient and the DC component of the preceding block. The difference is applied to a one-dimensional Huffman coding circuit 1402.
FIG. 33 is a detailed block diagram showing the DPCM 1401. In the DPCM 1401, the quantized DC coefficient from the quantization unit 1105 is applied to a delay circuit 1501 and a subtracter 1502. The delay circuit 1501 applies a delay equivalent to the time needed for the discrete cosine transformation circuit to operate on one block, namely 8.times.8 pixels. Accordingly, the delay circuit 1501 supplies the subtracter 1502 with the DC coefficient of the preceding block. As a result, the subtracter 54 outputs the differential (prediction error) between the current DC coefficient and that of the preceding block. (In this predictive coding, the value of the preceding block is used as the prediction value, and therefore the predicting unit is constituted by the delay circuit, as set forth above.)
In accordance with a DC Huffman code table 1403, the one-dimensional Huffman coding circuit 1402 applies variable-length coding to the prediction error signal supplied by the DPCM 1401 and supplies a DC Huffman code a multiplexer 1410.
An AC (alternating current) coefficient (a coefficient other than the DC coefficient) quantized by the quantization unit 1105 is zigzag-scanned in order from coefficients of lower order as shown in FIG. 34 by means of a scan converting circuit 1404, and the output of the scan converting circuit 1404 is applied to a non-zero coefficient detector circuit 1405. The latter determines whether the quantized AC coefficient is "0" or not. If the AC coefficient is "0", a count-up signal is supplied to a run-length counter 1406, thereby incrementing the counter.
If the coefficient is other than "0", however, a reset signal is applied to the run-length counter 1406 to reset the counter, and the coefficient is split into a group number SSSS and annexed bits, as shown in FIG. 37, by a grouping circuit 1407. The group number SSSS is supplied to a two-dimensional Huffman coding circuit 1408, and the annexed bits are supplied to the multiplexer 1410.
The run-length counter 1406 counts a run length of "0" and supplies the two-dimensional Huffman coding circuit 1408 with the number NNNN of "0"s between non-zero coefficients other than "0". In accordance with the Ac Huffman code table 1409, the two-dimensional Huffman coding circuit 1408 applies variable-length coding to the "0" run length NNNN and the non-zero coefficient group number SSSS and supplies the multiplexer 1410 with an AC Huffman code.
The multiplexer 1410 multiplexes the DC Huffman code, AC Huffman code and annexed bits of one block (8.times.8 input pixels) and outputs compressed image data from its output terminal 1411.
Accordingly, the compressed data outputted by the output terminal 1411 is stored in a memory, and at read- out the data is expanded by a reverse operation, thereby making it possible to reduce memory capacity.
In the example of the prior art described above, however, variable length coding (VLC) is used in the coding units (the one-dimensional Huffman coding circuit 1402 and two-dimensional Huffman coding circuit 1408). Consequently, the code length (information quantity) of one block of the DCT is not constant, and the correspondence between the memory addresses and the blocks is complicated. Executing the combining of images, such as the overlapping of images as shown in FIG. 35 and the partial overlaying of images as shown in FIG. 36, is very difficult to perform in memory.
In the frame memory of a page printer, this difficulty leads to a problem of a complicated correspondence between a frame address and block position on a page.
Further, in the example of the prior art described above, DPCM is used in the DC coefficient after DCT. Consequently, in a case where there is a partial block overlay, decoding must be performed retroactively back to the block at which the prediction value of DPCM is reset (namely the block at which an operation between blocks has not been performed). In addition, overlaying of the DC coefficient must be performed up to the block at which the next DPCM is reset, in such a manner that the overlaying will not cause the prediction value at the time of coding to differ from that at the time of decoding. This complicates the processing procedure for combining images in memory and prolongs the necessary computation time, thereby making it even more difficult to combine images in memory.